The present invention relates in general to integrated circuits, and in particular to an input buffer circuit using low-voltage transistors, that is capable of receiving high-voltage logic levels.
To reduce power consumption there has been a growing trend in various fields of semiconductor technology (including memories, microprocessors, complex programmable logic devices, etc.) toward designing devices that have the core circuitry operating at lower power supply voltages. These circuits, however, still must be able to interface with other circuitry that run at higher voltage levels. For example, the core circuitry for a microprocessor may be designed to operate with a 3.3 volt or a 2.9 volt supply voltage, but the chip must be able to receive and process signals swinging between for example ground and +5 volts. The interface problem has been traditionally solved by level shifting circuitry that translate the voltage at the input/output (I/O) interface from one level to the other.
The voltage differential between the internal power supply levels and the external signal levels, however, has continued to grow as the power supply voltages for core circuitry drop to lower and lower levels. This has posed new challenges to the circuit designer. More specifically, the low voltage circuitry can be fabricated using a low voltage process that places limitations on maximum voltage levels under which a transistor can operate reliably. To prevent I/O transistors from experiencing high voltage stress, it is common to insert cascode transistors in series with the transistors that drive the I/O node. The cascode transistors are then typically biased by a reference voltage to split the total voltage between the several transistors.
This circuit technique works reliably up to a certain voltage differential. For example, with a fixed reference voltage of 1.65 volts biasing the cascode transistors of an output driver that runs off of a 3.3 volt supply, the I/O transistors in a 1.9 volt process still undergo voltage stress given overshoot or undershoot of about 0.8 volts.
Similarly, a typical input buffer is made up of an inverter with a PMOS pull-up transistor and an NMOS pull-down transistor that may be coupled between, for example, 1.9 volts and ground, in a 1.9 volt process. Given an input signal that swings between 0 and 3.3 volts, in the case of likely overshoot of, for example, 0.8 volts, the NMOS pull-down transistor experiences voltages much higher than 1.9 volts (i.e., 4.1 volts) and is therefore subject to oxide stress. In case of an undershoot of the input signal, the PMOS pull-up transistor would also undergo oxide stress. Traditional circuit techniques, therefore, fail to protect the low-voltage I/O transistors that interface with higher voltage signals.
There is a need for an input buffer circuit that can be implemented with low voltage transistors yet safely receives and detects the logic levels of a high voltage input signal.